Architecture Features
Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set)
Pipeline: 4-stage sequential pipeline
General register: 32 32-bit GPRs; 16 128-bit VGPRs
Cache: I-Cache: 8 KB/16 KB/32 KB/64 KB (size options); D-Cache: 8 KB/16 KB/32 KB/64 KB (size options)
Tightly-coupled memory (TCM): I-TCM: 4 KB to 1 MB (size options); D-TCM: 4 KB to 1 MB (size options)
Tightly-coupled memory slave interface: Independent TCM bus slave interface
Bus interface: Dual bus (system bus + peripheral bus)
Memory protection: 0 to 8 optional protection zones
Scalar computing engine: 32-bit operation width
Vector computing engine: 128-bit operation width
Tight coupling IP: Interrupt controller and timer
Floating point engine: Optional single-precision floating point unit
Featured Technology
Vector calculation engine: Improves computing parallelism, and accelerates application scenarios like AI
Low-latency tightly-coupled memory: Expands memory bandwidth, and adapts to data-intensive computing scenarios
High-performance unaligned memory access: Accelerates unaligned memory access, and adapts to DSP applications
Architecture Diagram
