E902

E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency. It can be further equipped with secure execution technology to enhance system security. It is suitable for application fields that are extremely sensitive to power consumption and cost, such as IoT and MCU.

Architecture Features

  • Instruction set: T-Head ISA (compatible with RV32EMC/RV32EC/RV32IMC)

  • Pipeline: 2-stage

  • Permission mode: Optional M state or M+U state

  • General register: 16 32-bit GPRs

  • Bus interface: Dual bus (instruction bus + data bus)

  • Memory protection: 0 to 16 optional protection zones

  • Tight coupling IP: Interrupt controller and timer

  • Multiplier: Optional slow multiplier and fast multipliers

Featured Technology

  • Secure execution technology: Resists any hardware and software attack, and increases system security

  • Low-power cache: Reduces system memory access latency, and improves memory efficiency

  • Dynamic adjustment of interrupt priority: Enhancing real-time system performance, and implementing interrupt priority inversion in specific scenarios

  • Single-cycle memory speculation execution: Makes full use of memory bandwidth, so that the processor is completely streamlined

Architecture Diagram

Industrial Applications