Architecture Features
Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set)
Pipeline: 3-stage
General register: 16 32-bit GPRs
Bus interface: Tri-bus (instruction bus + data bus + system bus)
Memory protection: 0 to 8 optional protection zones
Tight coupling IP: Interrupt controller and timer
Multiplier: Single-cycle multiplier
Featured Technology
Secure execution technology: Resists any hardware and software attacks, and increases system security
Low-power cache: Reduces system memory access latency, and improves memory efficiency
Interrupt response acceleration technology: Enhances the system's real-time performance to allow users to quickly enter the corresponding service program
Speculative memory access technology: Reduce branch processing overheads, and improve access efficiency
Architecture Diagram
