E802

E802 utilizes a 2-stage minimalistic pipeline and optimizes average and peak power consumption. It can be equipped with optional secure execution technology to enhance system security. It is suitable for application fields that are extremely sensitive to power consumption and cost, such as IoT and MCU.

Architecture Features

  • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set)

  • Pipeline: 2-stage

  • General register: 16 32-bit GPRs

  • Bus interface: Dual bus (instruction bus + data bus)

  • Memory protection: 0 to 8 optional protection zones

  • Tight coupling IP: Interrupt controller and timer

  • Multiplier: Optional slow multiplier and fast multipliers

Featured Technology

  • Secure execution technology: Resists any hardware and software attacks, and increases system security

  • Low-power cache: Reduces system memory access latency, and improves memory efficiency

  • Interrupt response acceleration technology: Enhances the system's real-time performance to allow users to quickly enter the corresponding service program

  • Control of average power consumption and peak power consumption: Adaptive to specific application scenarios with stringent requirements for power consumption

  • Resists any hardware and software attacks, and increases system security

Architecture Diagram

Industrial Applications