Compatible with RISC-V architecture, C910 adopts 12-stage superscalar pipeline and enhances its arithmetic operation, memory access and multi-core synchronization. Meanwhile, it is configured with standard memory management unit and can run Linux and other operating systems; with 3-issue and 8-executive deep out-of-order execution architecture and single/double-precision floating-point unit, the vector compute engine can be optional.
It is applicable to artificial intelligence, 5G, edge server and other areas that have very high performance requirements.
View Datasheet(PDF)
Architecture Features
Instruction set
(compatible with RV64GC[V])
Symmetric Multi-Processing , 1-4 cores per cluster
3-issue (superscalar), deep out-of-order
General purpose register
32 64-bit GPR, 32 64-bit FGPR, 32 128-bit VGPR
Two level caches;
Optional 32KB/64KB I-Cache;
Optional 32KB/64KB D-Cache;
Optional 128KB~8MB L2 cache
Cache check
ECC check or parity check
Bus interface
One 128-bit master interface
one 128-bit slave interface
Floating point engine
Support single-precision/double-precision
floating-point arithmetic
Sv39 memory management, 512/1024 TLB
table entry
Physical memory protection
Optional 0-16 protection regions
Performance monitoring unit
RISC-V standard performance monitoring unit
Vector compute engine
Double 128-bit computing width; support SIMD calculation of INT8/INT16/INT32/INT64 and FP16/FP32/FP64
Multi-core coherency
Four core shared L2 Cache, support cache data coherency
Interrupt controller
Support multi-core shared PLIC interrupt controller, support up to 1023 external interrupts
Support multi-core collaborative debugging
Performance monitoring
Support hardware performance monitoring unit
Slide left and right to view the architecture
Technical Features
Mixed branch processing
Mixed processing technology covering branching direction, branch address, function return address and indirect addressing prediction to improve
instruction fetch efficiency
Data prefetching
Multi-channel and multi-mode data prefetching technology to improve data bandwidth significantly
Rapid memory loading
Get memory access data in advance, reduce
load-to-use latency
Memory speculative access prediction
Predict memory out-of-order speculative access, improve execution efficiency
Please log in Technical Resources for more details >