C906
Compatible with RISC-V architecture, C906 adopts standard memory management unit and can run Linux and other operating systems. C906 is designed with 5-stage integer pipeline and is optional with high-performance single/double-precision floating point and 128-bit vector computing unit. It is applicable to consumer IPC, multimedia, consumer electronics and other application areas.
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Architecture Features
Instruction set
XuanTie ISA
(compatible with RV64IMA[F][D]C[V])
Microarchitecture
Single-issue in-order execution, 5-stage integer pipeline
General purpose register
32 64-bit GPR, 32 64-bit FGPR, 32 128-bit VGPR
Vector execution unit
RISC-V Vector Extension to support SIMD
calculation of INT8/INT16/INT32/INT64 and FP16/FP32/FP64 and BFP16 new data format
Cache
Optional I-Cache and D-Cache, 8-64KB
Mixed branch prediction
Optional 8Kb/16Kb branch history table, branch target buffer and return address stack
Bus interface
128-bit single bus access interface
MMU
Sv39 memory management, 128/256/512 TLB table entry
Physical memory protection
Optional 0-16 protection regions
Interrupt
PLIC interrupt controller to support up to 1023 external interrupts
Performance monitoring unit
RISC-V standard performance monitoring unit
Debugging
Support RISC-V Debug protocol standard,
support IAR, Segger, Lauterbach and other third party IDE/debugging software
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basic
configurable
Technical Features
XMAE (XuanTie Memory Attribute Extension)
technology for memory management
Data prefetching
Multi-channel and multi-mode data prefetching technology to improve data bandwidth significantly
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