C810

C810 utilizes a 10-stage superscalar pipeline, with a standard memory management unit, and can run Linux and other operating systems. C810 utilizes a 2-issue and 5-execution out-of-order execution architecture with a single/double-precision floating point engine. It can be further equipped with other functions such as a high-performance vector calculation engine and secure execution technology. It is suitable for application fields requiring high processor performance such as secure monitoring and artificial intelligence.

Architecture Features

  • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set)

  • Pipeline: 10-stage

  • Microarchitecture: Dual-issue, out-of-order

  • General register: 32 32-bit GPRs; 16 128-bit VGPRs

  • Cache: 2-stage cache; I-cache: 16 KB/32 KB/64 KB (size options); D-cache: 16 KB/32 KB/64 KB (size options)

  • Bus interface: Dual bus (system bus + peripheral bus)

  • Memory protection: On-chip memory management unit supports hardware backfilling

  • Floating point engine: Supports single and double precision floating point operations

  • Vector calculation engine: 128-bit operation width, supporting 8-bit/16-bit/32-bit shaping and fixed-point parallel computing

  • Secure execution technology: Hardware assisted build of a secure execution environment

  • Performance monitoring: Supports a hardware performance monitoring unit

Featured Technology

  • High-Performance memory access: Supports out-of-order memory access, data prefetch and write combining to further expand memory bandwidth

  • Hybrid branch processing: Hybrid branch processing technology including branch direction, branch target address and function return address prediction to improve fetching efficiency

  • Vector calculation engine: Improves computing parallelism, and speeds up typical scenarios such as DSP and multimedia

  • Secure execution technology: Resists any hardware and software attacks, and increases system security

Architecture Diagram

Industrial Applications