Architecture Features
Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set)
Pipeline: 8-stage
Microarchitecture: Dual-issue, lightweight, out-of-order
General register: 32 32-bit GPRs
Cache: I-cache: 16 KB/32 KB/64 KB (size options); D-cache: 16 KB/32 KB/64 KB (size options)
Bus interface: Dual bus (system bus + peripheral bus)
Memory protection: On-chip memory management unit supports hardware backfilling
Floating point engine: Supports single and double precision floating point operations
Featured Technology
Lightweight out-of-order execution: Lightweight out-of-order execution architecture based on a distributed reservation station to improve instruction-level parallelism
Low power cache access: Cache access filter to reduce the power consumption during operation
Hybrid branch processing: Hybrid processing technology including branch direction, function return address and indirect jump address prediction to improve fetching efficiency
Architecture Diagram
