R807
R807 adopts 8-stage pipeline, dual-issue superscalar architecture and standard memory protection unit and achieves outstanding performance per watt by using the lightweight out-of-order execution architecture and speculative execution technology. Meanwhile, R807 is optimized in terms of deterministic memory accesses, peripheral latency, and interrupt response and so on, which is applicable to storage, industrial control and other areas that have very high requirements on real-time characteristics.
Architecture Features
Instruction set
XuanTie ISA
(32-bit/16-bit variable-length instruction system)
Pipeline
8-stage
Microarchitecture
dual-issue, lightweight out-of-order
General purpose register
32 32-bit GPR
Caches
Optional 16KB-64KB I-Cache
Optional 16KB-64KB D-Cache
TCM
Optional 4KB-1MB I-TCM, with configurable
1-2 cycle access latency;
Optional 4KB-1MB D-TCM, with configurable
1-2 cycle access latency;
Memory ECC check is supported
Bus interface
Double bus master interface, including system bus low latency peripheral bus, and TCM slave interface
Floating point engine
Support single-precision/double-precision
floating-point arithmetic
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basic
configurable
Technical Features
High real-time design
Optimized interrupt response delay available for
interrupting multi-cycle instruction execution and
responding to interrupt
Lightweight out-of-order execution
Lightweight out-of-order execution architecture based on distributed reservation station to improve instruction parallelism
Low-power cache access
High-speed cache access filter to reduce power consumption during operation
Mixed branch processing
Mixed processing technology covering branching direction, function return address, indirect addressing prediction to improve instruction fetch efficiency
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