Compatible with RISC-V architecture, E907 is a processor core with the best performance in XuanTie MCU processors.
E907 is mainly designed for voice portal MCU, TWS, MPU, navigation, multi-mode wireless access and other application areas.
View Datasheet(PDF)
Architecture Features
Instruction set
XuanTie ISA
(compatible with RV32IMA[F][D]C[P])
Single-issue in-order execution, integer
5-stage/floating-point 7-stage pipeline
General purpose register
32 32-bit GPR, 32 32-bit/64-bit FGPR
Optional I-Cache and D-Cache, 2K-32KB
Mixed branch prediction
Branch history table, branch target buffer and return address stack, with configurable sizes
Bus interface
Double bus interfaces, 1 master interface and
1 low-latency peripheral interface
Memory protection
Optional 0-16 protection regions
Memory access
Support unaligned memory read/write
CLIC interrupt controller, up to 240 interrupts
Performance monitoring unit
RISC-V standard performance monitoring unit
Support RISC-V Debug protocol standard,
support IAR, Segger, Lauterbach and other third party IDE/debugging software
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Technical Features
XIAE (XuanTie Interrupt Acceleration Extension) technology for fast interrupt response and processing
XMFF (XuanTie MCU Feature Extension)
technology for MCU applications
XMIE (XuanTie MCU ISA Extension)
technology for enhanced performance
Double-precision floating point computing
acceleration for navigation and other applications
MCU application-oriented memory access
enhancement technology to improve access
capability such as memory copy
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