Compatible with RISC-V architecture, E906 adopts 5-stage integer pipeline and is optional with high-performance single-precision or single/double-precision floating point units and 32-bit scalar DSP computing unit, which is applicable to wireless access, audio, TWS, middle- and high-end MCU, navigation and other application areas.
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Architecture Features
Instruction set
XuanTie ISA
(compatible with RV32IMA[F][D]C[P])
Single-issue in-order execution, 5-stage integer pipeline
General purpose register
32 32-bit GPR, 32 32-bit/64-bit FGPR
Optional I-Cache and D-Cache, 0-32KB
Mixed branch prediction
Branch history table, branch target buffer and return address stack, with configurable sizes
Bus interface
3 bus interfaces
(instruction bus data bus system bus)
Memory protection
Optional 0-16 protection regions
CLIC interrupt controller, up to 240 interrupts
Performance monitoring unit
RISC-V standard performance monitoring unit
Support RISC-V Debug protocol standard,
support IAR, Segger, Lauterbach and other 3rd party IDE/debugging software
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Technical Features
XIAE (XuanTie Interrupt Acceleration Extension) technology for fast interrupt response and processing
XMFF (XuanTie MCU Feature Extension)
technology for MCU applications
XMIE (XuanTie MCU ISA Extension)
technology for enhanced performance
Double-precision floating point computing
acceleration for navigation and other applications
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