Compatible with RISC-V architecture, E902 adopts 2-stage extremely simple pipeline and enhances its execution efficiency and can enhance
system security by the optional secure execution environment. It is applicable to IoT, MCU and other areas that are extremely sensitive to
power consumption and cost.
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Architecture Features
Instruction set
XuanTie ISA (compatible with RV32E[M]C)
2-stage pipeline
Privilege modes
M U modes
General purpose register
16 32-bit GPR
Bus interface
Double bus (instruction bus data bus)
Memory protection
Optional 0-16 protection regions
Tightly coupled IP
Interrupt controller, timer
Optional slow or fast multiplier
Gate count
~10K gates for the minimum configuration
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Technical Features
Secure execution environment
Resist various software and hardware attacks,
enhance system security
Low-power cache
Reduce system memory access delay,
improve memory performance
Interrupt priority dynamic adjustment
Enhance system real-time characteristics, realize interrupt priority inversion in specific scenarios
Single-cycle memory speculative access
Make full use of memory bandwidth, improve
processor CPI (cycle per instruction)
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