E804
E804 adopts 4-stage pipeline, scalar DSP compute engine and optional floating-point unit and secure execution environment,
which is applicable areas that have a certain requirement on computing power, such as audio, voice, motor control and so on.
Architecture Features
Instruction set
XuanTie ISA
(32-bit/16-bit variable-length instruction system)
Pipeline
4-stage pipeline
General purpose register
32 32-bit GPR
Bus interface
3 bus (instruction bus data bus system bus)
Memory protection
Optional 0~8 protection regions
Tightly coupled IP
Interrupt controller, timer
Floating point engine
Single-precision floating-point unit
DSP engine
32-bit Mini SIMD compute engine to support
8-bit/16-bit SIMD computing and 32-bit DSP computing
Slide left and right to view the architecture
basic
configurable
Technical Features
Secure execution environment
Resist various software and hardware attacks,
enhance system security
Low-power cache
Reduce system memory access delay,
improve memory performance
Interrupt priority dynamic adjustment
Enhance system real-time characteristics, realize interrupt priority inversion in specific scenarios
Short loop acceleration technology
Improve the processing capacity of short loops,
realize zero-loss branch processing
Data prefetch technology
Improve bus bandwidth utilization, adapt to massive data application scenarios
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