E803 adopts 3-stage in-order pipeline to realize the balance of performance and cost and enhances system security by optional secure execution environment, which is applicable to MCU, wireless access and other areas that are sensitive to cost and power consumption and have a certain requirement on performance.
Architecture Features
Instruction set
XuanTie ISA
(32-bit/16-bit variable-length instruction system)
3-stage pipeline
General purpose register
16 32-bit GPR
Bus interface
3 bus (instruction bus data bus system bus)
Memory protection
Optional 0~8 protection regions
Tightly coupled IP
Interrupt controller, timer
Single-cycle multiplier
Slide left and right to view the architecture
Technical Features
Secure execution environment
Resist various software and hardware attacks,
enhance system security
Low-power cache
Reduce system memory access latency,
improve memory performance
Interrupt response acceleration technology
Enhance system real-time characteristics,
rapidly enter interrupt service routine
Speculative memory access technology
Reduce branch processing overhead,
improve instruction fetch efficiency
Please log in Technical Resources for more details >