E802 adopts 2-stage extremely simple pipeline, optimizes its average and peak power consumption and enhances system security by optional secure execution environment, which is applicable to IoT, MCU and other application areas
that are extremely sensitive to power consumption and cost.
Architecture Features
Instruction set
XuanTie ISA
(32-bit/16-bit variable-length instruction system)
2-stage pipeline
General purpose register
16 32-bit GPR
Bus interface
Double bus (instruction bus data bus)
Memory protection
Optional 0~8 protection regions
Tightly coupled IP
Interrupt controller, timer
Optional slow or fast multiplier
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Technical Features
Secure execution environment
Resist various software and hardware attacks,
enhance system security
Low-power cache
Reduce system memory access latency,
improve memory performance
Interrupt response acceleration technology
Enhance system real-time characteristics,
rapidly enter interrupt service routine
Average and peak power consumption control
Applicable to the specific application scenarios with stringent requirements on power consumption
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