C910
Compatible with RISC-V architecture, C910 adopts 12-stage superscalar pipeline and enhances its arithmetic operation, memory access and multi-core synchronization. Meanwhile, it is configured with standard memory management unit and can run Linux and other operating systems; with 3-issue and 8-executive deep out-of-order execution architecture and single/double-precision floating-point unit,
It is applicable to artificial intelligence, 5G, edge server and other areas that have very high performance requirements.
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C910 Industry Applications
Mixed branch processing
Mixed processing technology covering branching direction, branch address, function return address and indirect addressing prediction to improve
instruction fetch efficiency
Data prefetching
Multi-channel and multi-mode data prefetching technology to improve data bandwidth significantly
Rapid memory loading
Get memory access data in advance, reduce
load-to-use latency
Memory speculative access prediction
Predict memory out-of-order speculative access, improve execution efficiency
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Industry Applications
Computer Vision
Intelligent Identification
Information Security
Architecture Features
Instruction set
XuanTieISA
(compatible with RV64GC)
Multi-core
Symmetric Multi-Processing , 1-4 cores per cluster
Pipeline
12-stage
Microarchitecture
3-issue (superscalar), deep out-of-order
General purpose register
32 64-bit GPR
32 64-bit FGPR
Cache
Two level caches;
Optional 32KB/64KB I-Cache;
Optional 32KB/64KB D-Cache;
Optional 128KB~8MB L2 cache
Cache check
ECC check or parity check
Bus interface
One 128-bit master interface
one 128-bit slave interface
Floating point engine
Support single-precision/double-precision
floating-point arithmetic
MMU
Sv39 memory management, 512/1024 TLB
table entry
Physical memory protection
Optional 0-16 protection regions
Performance monitoring unit
RISC-V standard performance monitoring unit
Multi-core coherency
Four core shared L2 Cache, support cache data coherency
Interrupt controller
Support multi-core shared PLIC interrupt controller, support up to 1023 external interrupts
Debugging
Support multi-core collaborative debugging
Performance monitoring
Support hardware performance monitoring unit
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basic
configurable
Technical Features
Mixed branch processing
Mixed processing technology covering branching direction, branch address, function return address and indirect addressing prediction to improve
instruction fetch efficiency
Data prefetching
Multi-channel and multi-mode data prefetching technology to improve data bandwidth significantly
Rapid memory loading
Get memory access data in advance, reduce
load-to-use latency
Memory speculative access prediction
Predict memory out-of-order speculative access, improve execution efficiency
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