C810
C810 adopts 10-stage superscalar pipeline and standard memory management unit and can run Linux and other operating systems;
with the dual-issue 5-executive out-of-order execution architecture and single/double-precision floating-point unit, the high-performance vector compute engine can be optional.
It is applicable to security surveillance, artificial intelligence and other application areas that have high requirements on processor performance
Architecture Features
Instruction set
XuanTie ISA
(32-bit/16-bit variable-length instruction system)
Pipeline
10-stage
Microarchitecture
Dual-issue, out-of-order
General purpose register
32 32-bit GPR
16 128-bit VGPR
Caches
Optional 16KB-64KB I-Cache
Optional 16KB-64KB D-Cache
Bus interface
Double bus (system bus peripheral bus) interface
Floating point engine
Support single-precision/double-precision
floating-point arithmetic
Vector compute engine
128-bit computing width, support SIMD
calculation of INT8/INT16/INT32/INT64 and FP16/FP32/FP64
Performance monitoring
Support hardware performance monitoring unit
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basic
configurable
Technical Features
High-performance memory access
Support out-of-order memory access, data prefetching, write combining and other technologies, further expand memory bandwidth
Mixed branch processing
Mixed processing technology covering branching direction, branch target address, function return
address prediction to improve instruction fetch efficiency
Vector compute engine
Improve computing parallelism, accelerate DSP/multimedia and other typical scenarios
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