C860
C860 adopts 12-stage superscalar pipeline and standard memory management unit and can run Linux and other operating systems; with the 3-issue and 8-executive out-of-order execution architecture, and single/double-precision floating-point unit, the high-performance vector compute engine can be optional. It is applicable to intelligent surveillance, machine vision, edge computing and other application areas that have very high requirements on processor performance.
View Datasheet(PDF)
C860 Industry Applications
Vector acceleration engine
Provide special acceleration instructions applicable to various neural networks and data types
Mixed branch processing
Mixed processing technology covering branching direction, branch address, function return address and indirect addressing prediction to improve
instruction fetch efficiency
Data prefetching
Multi-channel and multi-mode data prefetching technology to improve data bandwidth significantly
Slide left and right to view the architecture
Industry Applications
Computer Vision
Intelligent Identification
Architecture Features
Instruction set
XuanTie ISA
(32-bit/16-bit variable-length instruction system)
Multi-core
Symmetric Multi-Processing , 1~4 cores optional
Pipeline
12-stage
Microarchitecture
3-issue, deep out-of-order
General purpose register
32 32-bit GPR
16 128-bit VGPR
Caches
Two level high-speed caches;
Optional 32KB/64KB I-Cache;
Optional 32KB/64KB D-Cache;
Optional 128KB-2MB L2 Cache
Cache check
ECC or parity
Bus interface
One 128-bit master interface
one 128-bit slave interface
Floating point engine
Support single-precision/double-precision
floating-point arithmetic
Vector compute engine
Dual 128-bit computing width;
support SIMD calculation of
INT8/INT16/INT32/INT64 and FP16/FP32/FP64
acceleration instruction for
GEMM/FFT/FIR/IIR and other arithmetic
Multi-core coherency
Multi cores shared L2 Cache, support cache consistency
Interrupt controller
Support multi-core shared interrupt controller
Debugging
Support multi-core collaborative debugging
Performance monitoring
Support hardware performance monitoring unit
Slide left and right to view the architecture
basic
configurable
Technical Features
Vector acceleration engine
Provide special acceleration instructions applicable to various neural networks and data types
Mixed branch processing
Mixed processing technology covering branching direction, branch address, function return address and indirect addressing prediction to improve
instruction fetch efficiency
Data prefetching
Multi-channel and multi-mode data prefetching technology to improve data bandwidth significantly
Please log in Technical Resources for more details >